56
8008H–AVR–04/11
ATtiny48/88
selected, the low level must be held until the completion of the currently executing instruction to
generate an interrupt.
9.3.2
EIMSK – External Interrupt Mask Register
Bits 7:2 – Res: Reserved Bits
These bits are unused in ATtiny48/88, and will always read as zero.
Bit 1 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control bits (ISC11 and ISC10) in the External
Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising
and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt
request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt
Request 1 is executed from the INT1 Interrupt Vector.
Bit 0 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control bits (ISC01 and ISC00) in the External
Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising
and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt
request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt
Request 0 is executed from the INT0 Interrupt Vector.
9.3.3
EIFR – External Interrupt Flag Register
Bits 7:2 – Res: Reserved Bits
These bits are reserved and will always read zero.
Bit 1 – INTF1: External Interrupt Flag 1
When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set
(one). If the I-bit in SREG and the INT1 bit in EIMSK are set (one), the MCU will jump to the cor-
Table 9-3.
Interrupt 0 Sense Control
ISC01
ISC00
Description
0
The low level of INT0 generates an interrupt request.
0
1
Any logical change on INT0 generates an interrupt request.
1
0
The falling edge of INT0 generates an interrupt request.
1
The rising edge of INT0 generates an interrupt request.
Bit
76543
210
–––––
INT1
INT0
EIMSK
Read/Write
RR
RRRR
R/W
Initial Value
00000
000
Bit
76543
210
–––––
INTF1
INTF0
EIFR
Read/Write
RR
RRRR
R/W
Initial Value
00000
000
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